2017 Technical Webinar
ESD and Efficient Electronic Design – Finding and Fixing Problems at the IC Level
Overview:
Imagine, your production-ready electronic device has just failed an ESD test. Wouldn’t it have been better to discover and solve this problem much earlier, during the initial design cycle?
In this webinar we will discuss the impact of IC behavior on electronic design, specifically the characteristics of ESD and how they influence a device by influencing the ICs. To identify ESD problems, a special test setup must be used to recreate the disturbance at the IC level during the design process. This will save the engineer developing time and effort. Some ESD problems will be explained and supplemented by a practical example at both the electronic and IC level.
Who Should Attend?:
Developers, Designers, Engineers, Test Lab Engineers
Sven König, Dipl.-Ing. (BA)
After finishing High School, Sven studied (very successfully) electrical engineering. During his studies he gained practical experiences in EMC/EMI developing electronical devices. Having finished his scholastics he advanced experiences in different small sized enterprises. In 2007 Sven joined the team of Langer EMV-Technik GmbH as developing engineer. Langer EMV-Technik GmbH is an electro technical company that is active in the field of electromagnetic compatibility-related research, development and production of measurement tools. Sven is currently involved in the development of new measurement tools, practical troubleshooting on electronic devices, EMC/ESD tests on IC´s, teaching the effects of EMC and ESD in Langer EMV-Technik seminars and competent customer care.
Q&A
The following questions were asked during the live presentation. Click each question to view its answer.
How do we improve imunity on the ICs?
There are many possibilities for improving the immunity of ICs, some of which can be done by the IC designer and some of which can be done by the electronic developers on the PCB level. Such modifications at the PCB level include: shielding, filtering traces, changing layout, and so on…
Hello, in the page ESD characteristics what does that angle 30 deg, 45 deg, 90 deg in the plot "NSG435" mean
It is the angle of the ESD gun to the reference plane.
In the slide where you're interpreting test results, does the additional protection of the IC have to be internal (re-design) or may it be external?
Unless the IC designer modifies the IC itself, any additional modifications can only be external.
In the slide where you're interpreting test results, does the additional protection of the IC have to be internal (re-design) or may it be external?
Unless the IC designer modifies the IC itself, any additional modifications can only be external.
If components are received in a non anti static packaging. There is a risk that these might be gotten charged due to internal unsafe environment. How could we prevent CDM (charged device model) event to happen?
Unfortunately I don’t have an answer for you, as this webinar concerns components after they have been assembled onto the PCB.